code logs -> 2009 -> Fri, 24 Jul 2009< code.20090723.log - code.20090725.log >
--- Log opened Fri Jul 24 00:00:05 2009
00:00 AnnoDomini [~farkoff@Nightstar-29723.neoplus.adsl.tpnet.pl] has quit [Quit: Tradition may be defined as an extension of the franchise. Tradition means giving votes to the most obscure of all classes, our ancestors. It is the democracy of the dead. Tradition refuses to submit to the small and arrogant oligarchy of those who merely happen to be walking about. All democrats object to men being disqualified by the accident of birth; tradition objects to their being disqualified by the accident of death.]
00:00
<@ToxicFrog>
Fuck yes: http://pastebin.ca/1504985
00:01
<@TheWatcher>
... that's what I think it is, isn't it?
00:01
<@ToxicFrog>
Yes.
00:01
<@ToxicFrog>
It is.
00:01
<@TheWatcher>
Awesome :)
00:02
<@ToxicFrog>
It's not as pretty as the old shockmap output, but the code is much cleaner and is based on a general library for manipulating System Shock maps.
00:02
<@ToxicFrog>
Next for the library is object lists, and next for the program is postscript output.
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06:25
<@ToxicFrog>
Ok.
06:25
<@ToxicFrog>
I need a syntax for specifying bitfield (un)packs in my struct library.
06:25
<@ToxicFrog>
They need to convey the toplevel data type, and all the contents.
06:27
<@ToxicFrog>
Something like u2[U6 U5 U5] for a uint16_t containing three ints packed as 6,5,5 bits, say.
06:27
<@ToxicFrog>
Only less ugly
06:29
<@ToxicFrog>
Note that ({*:.}) are already reserved characters.
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06:46
<@Vornicus>
( and {, or is that a grouper.
06:50
<@ToxicFrog>
() is grouping and {} is packing.
06:52
<@Vornicus>
So ( and { are both reserved.
06:52
<@Vornicus>
(I was wondering at quoting)
06:52
<@ToxicFrog>
I did say.
06:53
<@Vornicus>
Now, as in I thought (blarg) meant that b, l, a, r, and g were reserved.
06:53
<@ToxicFrog>
Aah.
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10:15 * OperatorAbu mumbles at Verilog.
10:17
< OperatorAbu>
I have something like "outsignal <= (one + two + three + four)>48;" It seems to be an inline comparison, with the output being written to the outsignal.
10:17
< OperatorAbu>
But it behaves strangely.
10:18
< OperatorAbu>
It's 1 when the sum is >48, yes, but it also flickers a lot when signals change.
10:33
< OperatorAbu>
I take that back. The Verilog implementation works right. My VHDL translation worked wrong, since I assumed, stupidly, that with all the damned arithmetic libraries I reflexively include, it could parse bit vector addition as, well, the addition of numbers.
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11:03
< OperatorAbu>
If there's something I hate, is how VHDL handles comparisons.
11:04
< OperatorAbu>
Generally, the only thing you can trust it to do right is to tell whether a single bit is 1 or 0.
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11:05
< OperatorAbu>
It should say something about this that I'm using Sherlock Holmes' adage to find where the problems lie.
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11:34
<@gnolam>
Well, it's not a programming language, it's a HDL.
11:36
<@gnolam>
My main gripe with VHDL is its inconsistency.
11:38
<@gnolam>
Different elements have different /syntax/, FFS.
11:45
< OperatorAbu>
FINALLY. I've been looking for this bug for months, and only now my third randomly-generated simulation actually shows that it EXISTS.
11:47
< OperatorAbu>
Also, what do you mean it's not a programming language?
11:47 * OperatorAbu is clueless, would like to know.
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20:53
<@McMartin>
Philosophical question regarding early question: I'm assuming that the bar we're using here is that something needs to be Turing-complete to be "a real programming language".
20:54
<@McMartin>
... should it have to be intentionally Turing-Complete? Should sendmail.conf count?
20:54
<@ToxicFrog>
It does but it shouldn't~
20:55
<@McMartin>
Lots of intentional ones (Hi, M4) do but shouldn't even if you require intentionality~
20:56
< AnnoDomini>
TC is 'can write self in it'?
20:57
<@McMartin>
TC is "can compute any of a large class of mathematical functions called 'Turing-Decidable'"
20:57
<@McMartin>
Which happens to be equivalent to every program we know how to specify formally in any system.
20:57
<@McMartin>
So yes, TC includes "can write self in it" but it's theoretically conceivable to come up with a language that could write itself but not be that general.
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22:50
<@gnolam>
Actually, for me it's just that HDLs are just that: hardware description languages. You're not writing code. You're specifying hardware. Try to write VHDL like C and the end result, if it fits at all into the PLD/FPGA, will be shite.
22:50
<@gnolam>
... and he's already left. Crap.
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--- Log closed Sat Jul 25 00:00:20 2009
code logs -> 2009 -> Fri, 24 Jul 2009< code.20090723.log - code.20090725.log >